michaeljclark
commented
6 years ago @palmer-dabbelt @sagark @bkoppelmann @mcnamarad1971
I'd like to create a riscv-next branch, where we can stage active development like we do for the other riscv projects. I'd also like to create an upstream branch that we can use to rebase riscv-next against so we can sync with upstream.
For this small change, I'm debating whether we just merge it on the basis that it cleans up a coupling issue. i.e. it gets master into a cleaner state and it's a low-risk change as it only affects code that uses SiFiveUART in interrupt-driven mode, which is essentially none i.e. is waiting for a test case.
In either case, I'd like this change to be in our upstream patch set. Technically we need linux-kernel/drivers/tty/serial/sifive_uart.c to test out this device, and the uart emulation will undoubtedly need more work, but decoupling devices from the PLIC using qemu_irq as per virtio and the 16550a makes sense. i.e. we shouldn't have any devices directly coupled to the PLIC. The code this commit alters was written before we'd figured out how to attach devices to the PLIC. Indeed the U54 pull request had a copy of hw/char/serial.c modified to wire interrupts directly to the PLIC (see https://github.com/riscv/riscv-qemu/pull/70/commits/924f9deb63b896753657249ad677ca8670cd9d55). I'd mistakenly followed that example. Now we are using the unmodified 16550a implementation in hw/char/serial.c wired via to the PLIC indirectly using the PLIC's array of qemu_irqs, which is not only much cleaner, it's the right way to wire a device to an interrupt controller in QEMU. It allows us to use the device with a different interrupt controller.
So this is not a bug fix per se, it's a coupling/design issue. i.e. plumbing cleanup.
The only remaining feature in the U54 PR https://github.com/riscv/riscv-qemu/pull/70 that we don't have in master is TIM (L1 cache ways as memory) and the 4+1 CPU topology. All of the priv1.10 changes in PR https://github.com/riscv/riscv-qemu/pull/70 have been merged.
So I can merge this PR, or close this PR and move the commit to a riscv-next branch...
This just cleans up the attachment of SiFiveUART interrupts by decoupling it from the PLIC.
We don't have any code currently using the SiFiveUART with interrupts so this change doesn't affect anything. It just makes it possible to use the UART with any interrupt controller, much like the QEMU's serial.c which we connect to the PLIC using qemu_irq.
Once we have a drivers/tty/serial/sifive_uart.c in linux-kernel we can test interrupts...