Closed rtcw50 closed 6 years ago
This behavior is, as far as I know, correct. The cycle counter is read-only in RISC-V (see the privileged specification), and so writes to it are decoded as illegal instructions; qemu-system-riscv32 will take an illegal instruction trap in the guest, while user emulation does the equivalent of a raise(SIGILL) to allow signal handlers within the emulated program to fire.
OK, thanks, now that I think about it, that seems reasonable. Sorry for the interrupt.
Hello, RISCV QEMU seems unable to execute csrrw instructions. Assembly encoding seems ok to me. Thanks for the help.
ENVIRONMENT Ubuntu 1604 docker image (reproduced on Fedora 23 native as well)
QEMU:
RISCV gcc:
RISCV Clang:
Compile the following code with gcc or clang:
riscv32-unknown-elf-gcc csrrw.c -o csrrw.elf
csrrw.c:
Execute in user mode:
... rv-tools/riscv-qemu/build/riscv32-linux-user/qemu-riscv32 csrrw.elf
Output:
Illegal instruction (core dumped)
Debug Output: