Hardware Performance Monitor Privileged V1.10 Support

[song10]

My riscv-qemu HEAD is 05e0ed

The read access logic for CRS_INSTRET, and CSR_CYCLE are priv-1.9.1 only, though HPM CSRs for both priv-1.9.1 and priv-1.10 are there.

[michaeljclark]

Can you be more specific about what the particular issue is?

The HPM CSRs all return 0, if enabled and where introduced in privileged ISA v1.9.1.

There have been changes in this area recently, towards spec compliance. Can you try this branch:

• https://github.com/riscv/riscv-qemu/tree/riscv-wip

CSR_TIME/CSR_TIMEH are now emulated by bbl the same way as spike handles them.

[NonerKao]

@michaeljclark I checkout the branch. To be specific:

• mucounteren and mscounteren still exist. Not only that, some access logic relies on them, which causes the expected priv-1.10 behavior not shown.
• The pirv-1.10 Spec does not mention whether the write to mcycle[h], minstret[h] or mtime[h] is permitted or not, and this simulator has only "wrtie not implemented" messages in target/riscv/op_helper.c's csr_write_helper.

Any comments are appreciated.

[michaeljclark]

We've changed mcycle[h], minstret[h] and misa to discard writes and removing the messages. Writes to these registers are optional.

https://github.com/riscv/riscv-qemu/pull/115

Okay. I see what you mean now:

• priv-v1.9.1 has mscounteren and mucounteren
• priv-v1.10 has mcounteren and scounteren

Yes, it appears that we have the v1.9.1 behavior. It needs some conditional logic added to implement the priv-v1.10 behavior. We have both sets of variables but are missing the conditional logic to enable to disable the respective set of CSRs and to read the new CSRs in priv v1.10

I can work on a fix.

[NonerKao]

Thanks for the help. This is a critical feature for developing perf at this stage.

[michaeljclark]

There is a fix for this in the qemu-2.13-bug-fixes branch:

• https://github.com/riscv/riscv-qemu/tree/qemu-2.13-bug-fixes

[michaeljclark]

This is fixed in master (https://github.com/riscv/riscv-qemu/commit/8c59f5c1b5aabbad92871bf62bb302fef017e322) so closing this issue.

Note the new mcounteren/scounteren CSRs will now work correctly for privileged ISA v1.10 as the counteren state is now shared between privileged ISA v1.9.1 and v1.10, however, the unsupported performance counters will simply return 0. It should be enough to allow testing perf.