riscvarchive / riscv-v-spec

Working draft of the proposed RISC-V V vector extension
https://jira.riscv.org/browse/RVG-122
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Checks ordering: nop vs trap #912

Open ajayvreddy opened 1 year ago

ajayvreddy commented 1 year ago

Hi, I have a very basic question as to what should take higher precedence. If no instruction is performed for a certain configuration but it has illegal values for some other field. What should happen.

eg. for Vector reduction Operations, the spec mentions that: If vl=0, no operation is performed and the destination register is not updated..

so, for EEW >64 (illegal) and vl =0, should it take an exception or nop.