riscvarchive / riscv-zicond

The ISA specification for the ZiCondOps extension.
https://jira.riscv.org/browse/RVG-122
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pseudocode suggests that replaced sequence is longer than necessary #1

Closed jnk0le closed 1 year ago

jnk0le commented 1 year ago

The pseudocode suggest as if the proposed instructions were replacing 4 instruction sequence:

    beqz rs2, 1f
    mv rd, rs1
    j 2f
1:
    mv rd, zero
2:

even though it can be implemented in 3 instructions:

    mv rd, zero
    beqz rs2, 1f
    mv rd, rs1
1:

Of course it doesn't reflect exactly what those instructions are doing, but there is nowhere any mention about the sequence those instructions replace, so the pseudocode defacto takes its role.

ptomsich commented 1 year ago

This pseudocode is intended to clarify the semantic dependencies on the input operands: the zero-result is predictable from the value of $rs2.

Also note that the shorter sequence proposed does not work for regno(rd) == regno(rs1).

ptomsich commented 1 year ago

/close

jnk0le commented 1 year ago

Also note that the shorter sequence proposed does not work for regno(rd) == regno(rs1).

then the inverted sequence should work:

    mv rd, rs1
    bnez rs2, 1f
    mv rd, zero
1:

but in case of regno(rd) == regno(rs1) compilers would emit 2 instruction sequence instead:

    bnez rs2, 1f
    mv rd, zero
1:

I think that "equivalent sequences" could be covered by other chapter. Table in 2.1 is a one good place.