Closed XVilka closed 1 year ago
@Basstorm by the way, there are PDB tests that fail on the System-Z as well, please take a look:
[XX] db/formats/pdb GUID CHECK
RZ_NOPLUGINS=1 rizin -escr.utf8=0 -escr.color=0 -escr.interactive=0 -N -Qc '!rz-bin -I ${RZ_FILE} | grep -ao 15F778B3671D4EFDBDCDE79905308B792' bins/pdb/user32.dll
-- stdout
--- expected
+++ actual
@@ -1,1 +1,0 @@
-15F778B3671D4EFDBDCDE79905308B792
[XX] db/formats/pdb PDB downloader json
RZ_NOPLUGINS=1 rizin -escr.utf8=0 -escr.color=0 -escr.interactive=0 -N -Qc '%RZ_CURL=1
!rz-bin -PPj bins/pdb/user32.dll
' =
-- stdout
--- expected
+++ actual
@@ -1,1 +1,1 @@
-{"pdb":{"file":"user32.pdb","download":true}}
+{"pdb":{"file":"user32.pdb","download":false}}
-- stderr
Attempting to download compressed pdb in /home/travis/.local/share/rizin/pdb/user32.pdb/B378F7151D67FD4EBDCDE79905308B792000000/user32.pd_
Falling back to uncompressed pdb
Attempting to download uncompressed pdb in /home/travis/.local/share/rizin/pdb/user32.pdb/B378F7151D67FD4EBDCDE79905308B792000000/user32.pdb
[XX] db/formats/pdb idpdj
RZ_NOPLUGINS=1 rizin -escr.utf8=0 -escr.color=0 -escr.interactive=0 -N -Qc '%RZ_CURL=1
idpdj
' bins/pdb/user32.dll
-- stdout
--- expected
+++ actual
@@ -1,1 +1,1 @@
-{"pdb":{"file":"user32.pdb","download":true}}
+{"pdb":{"file":"user32.pdb","download":false}}
-- stderr
Attempting to download compressed pdb in /home/travis/.local/share/rizin/pdb/user32.pdb/B378F7151D67FD4EBDCDE79905308B792000000/user32.pd_
Falling back to uncompressed pdb
Attempting to download uncompressed pdb in /home/travis/.local/share/rizin/pdb/user32.pdb/B378F7151D67FD4EBDCDE79905308B792000000/user32.pdb
Error while downloading pdb file
[XX] db/formats/pdb PDB downloader check
RZ_NOPLUGINS=1 rizin -escr.utf8=0 -escr.color=0 -escr.interactive=0 -N -Qc '%RZ_CURL=1
!!rz-bin -PP ${RZ_FILE} ~PDB
' bins/pdb/user32.dll
-- stdout
--- expected
+++ actual
@@ -1,1 +1,1 @@
-PDB "user32.pdb" download success
+PDB "user32.pdb" download failed
-- stderr
Attempting to download compressed pdb in /home/travis/.local/share/rizin/pdb/user32.pdb/B378F7151D67FD4EBDCDE79905308B792000000/user32.pd_
Falling back to uncompressed pdb
Attempting to download uncompressed pdb in /home/travis/.local/share/rizin/pdb/user32.pdb/B378F7151D67FD4EBDCDE79905308B792000000/user32.pdb
this looks like a serious regression linked to endianness
@Rot127 a bunch of them are from PPC disassembly and uplifting:
[XX] db/asm/ppc_64 <asm> bne cr5
-- <asm> bne cr5 <--- 00009640 ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set CIA (bv 64 0x1a4)) empty empty (set NIA (ite (let bo (bv 5 0x4) (&& (|| (! (is_zero (& (bv 5 0x10) (var bo)))) (^^ (! (is_zero (& (var cr5) (bv 4 0x2)))) (! (! (is_zero (& (bv 5 0x8) (var bo))))))) (|| (! (is_zero (& (bv 5 0x4) (var bo)))) (^^ (! (is_zero (var ctr))) (! (is_zero (& (bv 5 0x2) (var bo)))))))) (bv 64 0x7) (+ (var CIA) (bv 64 0x4)))) (jmp (var NIA)))
+(seq (set CIA (bv 64 0x1a4)) empty empty (set NIA (ite (let bo (bv 5 0x4) (&& (|| (! (is_zero (& (bv 5 0x10) (var bo)))) (^^ (! (is_zero (& (var cr5) (bv 4 0x2)))) (! (! (is_zero (& (bv 5 0x8) (var bo))))))) (|| (! (is_zero (& (bv 5 0x4) (var bo)))) (^^ (! (is_zero (var ctr))) (! (is_zero (& (bv 5 0x2) (var bo)))))))) (bv 64 0x700000000) (+ (var CIA) (bv 64 0x4)))) (jmp (var NIA)))
[XX] db/asm/ppc_64 <asm> cmpldi cr7, r0, 1
-- <asm> cmpldi cr7, r0, 1 <--- 2ba00001 ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set l (var r0)) (set r (append (bv 48 0x0) (bv 16 0x1))) (set so_flag (ite (var so) (bv 1 0x1) (bv 1 0x0))) (branch (&& (ule (var l) (var r)) (! (== (var l) (var r)))) (set cr7 (append (bv 3 0x4) (var so_flag))) (branch (! (ule (var l) (var r))) (set cr7 (append (bv 3 0x2) (var so_flag))) (set cr7 (append (bv 3 0x1) (var so_flag))))))
+WARNING: ppc_cmp_set_cr: assertion 'left && right && crX' failed (line 46)
Invalid instruction of lifting not implemented.
[XX] db/asm/ppc_64 <asm> cmplwi cr6, r0, 0
-- <asm> cmplwi cr6, r0, 0 <--- 2b000000 ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set l (cast 64 (msb (cast 32 false (var r0))) (cast 32 false (var r0)))) (set r (cast 64 false (bv 16 0x0))) (set so_flag (ite (var so) (bv 1 0x1) (bv 1 0x0))) (branch (&& (ule (var l) (var r)) (! (== (var l) (var r)))) (set cr6 (append (bv 3 0x4) (var so_flag))) (branch (! (ule (var l) (var r))) (set cr6 (append (bv 3 0x2) (var so_flag))) (set cr6 (append (bv 3 0x1) (var so_flag))))))
+WARNING: ppc_cmp_set_cr: assertion 'left && right && crX' failed (line 46)
Invalid instruction of lifting not implemented.
[XX] db/asm/ppc_64 <asm> cmpld cr5, r0, r1
-- <asm> cmpld cr5, r0, r1 <--- 7ea00840 ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set l (var r0)) (set r (var r1)) (set so_flag (ite (var so) (bv 1 0x1) (bv 1 0x0))) (branch (&& (ule (var l) (var r)) (! (== (var l) (var r)))) (set cr5 (append (bv 3 0x4) (var so_flag))) (branch (! (ule (var l) (var r))) (set cr5 (append (bv 3 0x2) (var so_flag))) (set cr5 (append (bv 3 0x1) (var so_flag))))))
+WARNING: ppc_cmp_set_cr: assertion 'left && right && crX' failed (line 46)
Invalid instruction of lifting not implemented.
[XX] db/asm/ppc_64 <asm> cmpdi cr3, r0, 1
-- <asm> cmpdi cr3, r0, 1 <--- 2da00001 ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set l (var r0)) (set r (let v (bv 16 0x1) (ite (msb (var v)) (cast 64 (msb (var v)) (var v)) (cast 64 false (var v))))) (set so_flag (ite (var so) (bv 1 0x1) (bv 1 0x0))) (branch (&& (sle (var l) (var r)) (! (== (var l) (var r)))) (set cr3 (append (bv 3 0x4) (var so_flag))) (branch (! (sle (var l) (var r))) (set cr3 (append (bv 3 0x2) (var so_flag))) (set cr3 (append (bv 3 0x1) (var so_flag))))))
+WARNING: ppc_cmp_set_cr: assertion 'left && right && crX' failed (line 46)
Invalid instruction of lifting not implemented.
[XX] db/asm/ppc_64 <asm> cmplw cr4, r0, r1
-- <asm> cmplw cr4, r0, r1 <--- 7e000840 ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set l (cast 64 (msb (cast 32 false (var r0))) (cast 32 false (var r0)))) (set r (cast 64 (msb (cast 32 false (var r1))) (cast 32 false (var r1)))) (set so_flag (ite (var so) (bv 1 0x1) (bv 1 0x0))) (branch (&& (ule (var l) (var r)) (! (== (var l) (var r)))) (set cr4 (append (bv 3 0x4) (var so_flag))) (branch (! (ule (var l) (var r))) (set cr4 (append (bv 3 0x2) (var so_flag))) (set cr4 (append (bv 3 0x1) (var so_flag))))))
+WARNING: ppc_cmp_set_cr: assertion 'left && right && crX' failed (line 46)
Invalid instruction of lifting not implemented.
[XX] db/asm/ppc_64 <asm> cmpd cr5, r0, r1
-- <asm> cmpd cr5, r0, r1 <--- 7ea00800 ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set l (var r0)) (set r (var r1)) (set so_flag (ite (var so) (bv 1 0x1) (bv 1 0x0))) (branch (&& (sle (var l) (var r)) (! (== (var l) (var r)))) (set cr5 (append (bv 3 0x4) (var so_flag))) (branch (! (sle (var l) (var r))) (set cr5 (append (bv 3 0x2) (var so_flag))) (set cr5 (append (bv 3 0x1) (var so_flag))))))
+WARNING: ppc_cmp_set_cr: assertion 'left && right && crX' failed (line 46)
Invalid instruction of lifting not implemented.
[XX] db/asm/ppc_64 <asm> cmpw cr3, r0, r1
-- <asm> cmpw cr3, r0, r1 <--- 7d800800 ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set l (cast 64 (msb (cast 32 false (var r0))) (cast 32 false (var r0)))) (set r (cast 64 (msb (cast 32 false (var r1))) (cast 32 false (var r1)))) (set so_flag (ite (var so) (bv 1 0x1) (bv 1 0x0))) (branch (&& (sle (var l) (var r)) (! (== (var l) (var r)))) (set cr3 (append (bv 3 0x4) (var so_flag))) (branch (! (sle (var l) (var r))) (set cr3 (append (bv 3 0x2) (var so_flag))) (set cr3 (append (bv 3 0x1) (var so_flag))))))
+WARNING: ppc_cmp_set_cr: assertion 'left && right && crX' failed (line 46)
Invalid instruction of lifting not implemented.
[XX] db/asm/ppc_64 <asm> cmpwi cr2, r0, 0xffff
-- <asm> cmpwi cr2, r0, 0xffff <--- 2d00ffff ---> <IL>
-- IL
--- expected
+++ actual
@@ -1,1 +1,1 @@
-(seq (set l (cast 64 (msb (cast 32 false (var r0))) (cast 32 false (var r0)))) (set r (cast 64 (msb (bv 16 0xffff)) (bv 16 0xffff))) (set so_flag (ite (var so) (bv 1 0x1) (bv 1 0x0))) (branch (&& (sle (var l) (var r)) (! (== (var l) (var r)))) (set cr2 (append (bv 3 0x4) (var so_flag))) (branch (! (sle (var l) (var r))) (set cr2 (append (bv 3 0x2) (var so_flag))) (set cr2 (append (bv 3 0x1) (var so_flag))))))
+WARNING: ppc_cmp_set_cr: assertion 'left && right && crX' failed (line 46)
Invalid instruction of lifting not implemented.
This test: <asm> bne cr5 <--- 00009640 ---> <IL>
seems to be broken in Capstone (https://github.com/capstone-engine/capstone/issues/1914). The immediate operand is not filled and contains therefor unprocessed data.
Edit the others come from cs_reg_name
. It returns NULL
.
The current count is 147 tests: https://app.travis-ci.com/github/rizinorg/rizin/jobs/585102215
Full log sysz-failures.log
Work environment
Expected behavior
All green
Actual behavior
See https://app.travis-ci.com/github/rizinorg/rizin/jobs/586429352
See https://app.travis-ci.com/github/rizinorg/rizin/jobs/542280942
Mach-O file format parsing
PE file format parsing
MDMP file format parsing:
DMP file format parsing:
NE file format parsing
Likely most failures related to assuming the data is always little endian.
Running Linux on S390 in QEMU