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rizinorg / rz-hexagon

Hexagon disassembler code generator for Rizin from the LLVM definitions.
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RxIn registers have `REG_OUT` flag set. #59

Open Rot127 opened 2 years ago

Rot127 commented 2 years ago

Rx and RxIn are set separately in hi->ops although they are the same register (Rx registers are used for input and output). But the register attribute for RxIn is set to HEX_OP_REG_OUT although it is an "in" register.

The attribute is falsely assigned here: https://github.com/rizinorg/rz-hexagon/blob/7363e5945c93604ef0cca222cd9ca67029cf4d8c/InstructionTemplate.py#L217-L218

Currently the attributes are not used. So there is not much damage.