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rizinorg / rz-hexagon

Hexagon disassembler code generator for Rizin from the LLVM definitions.
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Remove duplicate imported instructions #81

Closed Rot127 closed 11 months ago

Rot127 commented 1 year ago

Multiple system instructions which we imported before are meanwhile added to LLVM. We should check if the opcode bits match and remove the imported versions if so. If they don't match we need to mark the previously IMPORTED instructions as UNDOCUMENTED.

List of potential duplicates.

[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_Rd_memw_locked_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_Rdd_memd_locked_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_barrier'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_brkpt'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_dccleana_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_dccleaninva_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_dcfetch_Rs__u11_3'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_dcinva_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_dczeroa_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_diag0_Rss_Rtt'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_diag1_Rss_Rtt'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_diag_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_icinva_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_isync'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_l2fetch_Rs_Rt'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_l2fetch_Rs_Rtt'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_memd_locked_Rs_Pd__Rtt'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_memw_locked_Rs_Pd__Rt'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_pause__u8'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_syncht'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_trace_Rs'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_trap0__u8'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_trap1_Rx__u8'
[*] Imported instruction was added to LLVM. Remove it if opcodes match. Instr.: 'IMPORTED_wait_Rs'