Open roberttylka opened 2 years ago
I want to report issues with descriptions (syntax and opcodes) in these chapters:
5.33 LURWU: a load word instruction that shifts 32 bits of registers and extends zero bits.
5.34 LWD: a load word instruction that loads double registers and extends signed bits.
LLVM disassembler shows one extra operand for:
lwd t1, t2, (t3), 2, 3 lwud t1, t2, (t3), 2, 3 ldd t1, t2, (t3), 2, 4 swd t1, t2, (t3), 2, 3 sdd t1, t2, (t3), 2, 4
instructions. Is it OK?
It looks like ok :)
I want to report issues with descriptions (syntax and opcodes) in these chapters:
5.33 LURWU: a load word instruction that shifts 32 bits of registers and extends zero bits.
5.34 LWD: a load word instruction that loads double registers and extends signed bits.
LLVM disassembler shows one extra operand for:
lwd t1, t2, (t3), 2, 3 lwud t1, t2, (t3), 2, 3 ldd t1, t2, (t3), 2, 4 swd t1, t2, (t3), 2, 3 sdd t1, t2, (t3), 2, 4
instructions. Is it OK?