rkharris12
commented
2 years ago You can try changing C_ROLL_FACTOR_LOG2 on line 76 of miner_top.vhd. Valid numbers are 0 - 6, and a higher number will generate a smaller design
Open beratiks opened 2 years ago
rkharris12
commented
2 years ago You can try changing C_ROLL_FACTOR_LOG2 on line 76 of miner_top.vhd. Valid numbers are 0 - 6, and a higher number will generate a smaller design
Hi rkharris, thanks for this project. I have digilent zybo z7-10 board and I synthesis succesfully. But I got error about LUT size. I think my fpga version a little bit lower than you. Do you have any comment about How can I run this system with my fpga? Can I reduce your design's resources? I attached my error logs below.
[Place 30-640] Place Check : This design requires more Register as Flip Flop cells than are available in the target device. This design requires 51243 of such cell types but only 35200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. [Place 30-640] Place Check : This design requires more Slice Registers cells than are available in the target device. This design requires 51243 of such cell types but only 35200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. [Place 30-640] Place Check : This design requires more Slice LUTs cells than are available in the target device. This design requires 51495 of such cell types but only 17600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning. [Place 30-640] Place Check : This design requires more LUT as Logic cells than are available in the target device. This design requires 51434 of such cell types but only 17600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning. [Place 30-640] Place Check : This design requires more FDCE cells than are available in the target device. This design requires 50613 of such cell types but only 35500 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. [Place 30-640] Place Check : This design requires more LUT3 cells than are available in the target device. This design requires 51757 of such cell types but only 35200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.