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rlindsberg / 1331IL-VHDL-Design

Microprocessor AR 4003
GNU General Public License v3.0
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Test bench for full adder fails #2

Closed rlindsberg closed 6 years ago

rlindsberg commented 6 years ago

numSum is always 0 no matter what values numA, numB, numCin has. See screenshot.

screen shot 2018-09-02 at 18 16 20 2

rlindsberg commented 6 years ago

Do you have any idea? @gitgnmn

gitgnmn commented 6 years ago

I got a similar problem actually. But my out values are U instead of 0. So I'm not even sure I'm using modelsim correct.

gitgnmn commented 6 years ago

Personally I'm going to see if I can get the example code from the exercise to work in modelsim before I start to bug hunt. (tomorrow, not today)

rlindsberg commented 6 years ago

In some of my simulating-runs I got also U, which I believe is undefined.

https://github.com/rlindsberg/1331IL-VHDL-Design/blob/13ee9fa7d2a3100f7fabcbfe9b169fe9fd7fab92/labb1/TB_full_adder.vhd#L25-L26

If only

Signal numCarry: std_logic; Signal numSum: std_logic;

They would have the value U...

rlindsberg commented 6 years ago

Sure. See you tomorrow!

rlindsberg commented 6 years ago

I solved the bug! @gitgnmn

rlindsberg commented 6 years ago

Right-click the file you want to bench -> Open.

screen shot 2018-09-04 at 08 07 09

Remember its entity name, in this case "full_adder".

screen shot 2018-09-04 at 08 07 29

Go to Assignments -> Settings -> General.

screen shot 2018-09-04 at 08 07 57 2

Click the "..." to the right of Top-level entity and select the entity from the second step.

screen shot 2018-09-04 at 08 09 42 2

RTL Simulation result:

screen shot 2018-09-04 at 08 06 17 2

gitgnmn commented 6 years ago

Awesome! I still have to finish my test benches before I can test fully.