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rlindsberg / 1331IL-VHDL-Design

Microprocessor AR 4003
GNU General Public License v3.0
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Simulation fails #26

Closed rlindsberg closed 6 years ago

rlindsberg commented 6 years ago

Error loading design:

screen shot 2018-09-11 at 00 17 25

No waves to show: screen shot 2018-09-11 at 00 17 07

rlindsberg commented 6 years ago

Multiple signals are Undefined

screen shot 2018-09-11 at 00 23 26

rlindsberg commented 6 years ago

Bug identified: no CLK signal