Preparations for lab 2 done, Simulation 50% passed

[rlindsberg]

closes #15 , closes #16 , closes #17 , closes #18 , closes #19 , closes #20 , closes #21 , closes #22 , closes #23 , closes #24

• Design CPU Package and ALU
• Write test bench for ALU
• Simulation 50% passed:
  1. 3 + 3, passed
  2. 4 - 3, passed
  3. 8 + 8 -> o_flag = 1, failed
  4. 8 - (-8) -> n_flag = 0; z_flag = 1, failed

[gitgnmn]

"8 + 8 -> o_flag = 1, failed" looks like it doesn't have enough time to propagate. So that might work.

8-(-8) shouldn't be im the test since we should be using signed numbers.

I think y should be 4 bits (data_size) and the carry is overflow.

Also I think all our in and out signals should be data_size or even be using data word.

[rlindsberg]

"8 + 8 -> o_flag = 1, failed" looks like it doesn't have enough time to propagate. So that might work.

In which statement do you think we should change the delay?

[rlindsberg]

8-(-8) shouldn't be im the test since we should be using signed numbers.

What do you think about 5-(-5)?

[rlindsberg]

I think y should be 4 bits (data_size) and the carry is overflow. Also I think all our in and out signals should be data_size or even be using data word.

I tried that, but got issue: cannot assign 4 bit to a 5 bit vector. Thus I changed y to 5 bits. This problem is coming from my design of cpu package in the very first commit. Chaning the type to data_size means a large rewrite of the logic. Wouldd't recommend.

We could just forget about the 5th bit in y but instead assign it to carry.

[gitgnmn]

We could just forget about the 5th bit in y but instead assign it to carry.

Yeah, I think this is the right way to go here.

[rlindsberg]

FANTASTIC! @gitgnmn

[rlindsberg]

Confirmed working by trust. Not tested. Merged