Lab 3 complete, simulation passed

[rlindsberg]

closes #29 , closes #34

Todos

• [x] A1.1 Register File
• [x] A1.1 TB
• [x] A1.2 Data Buffer
• [x] A1.2 TB
• [x] A1.3 MUX
• [x] A1.3 TB
• [x] A1.4 ROM
• [x] A1.4 TB
• [x] A1.5 RWM
• [x] A1.1 TB

For rw memory:

Test 1, 2:

-- test 1: write 1010 to mem(0000)
-- bring ce to low for 1 ns
-- bring rw to low for writing
-- bring ce to high
-- time: 6 ns
addr_in <= "0000";
ce_in <= '0';
rw_in <= '0';
Z_inout <= "1010";

wait for 1 ns;
Z_inout <= "ZZZZ";
ce_in <= '1';
wait for 5 ns;

-- test 2: write 1011 to mem(0001)
-- bring ce to low for 1 ns
-- bring rw to low for writing
-- bring ce to high
-- time: 6 ns
addr_in <= "0001";
ce_in <= '0';
rw_in <= '0';
Z_inout <= "1011";

wait for 1 ns;
Z_inout <= "ZZZZ";
ce_in <= '1';
wait for 5 ns;

Test 3 - 6:

-- test 3: read from mem(0000), expecting 1010
-- bring ce to low for 1 ns
-- keep rw at high for reading
-- bring ce to high
-- time: 6 ns
addr_in <= "0000";
ce_in <= '0';
rw_in<= '1';
wait for 1 ns;
ce_in <= '1';
wait for 5 ns;

-- test 4: write when ce is high
-- keep ce at high
-- bring rw to low
-- write 1100 to mem(0010)
-- set Z_inout to output
-- expect: UUUU at mem(0010)
-- time 4 ns, start 18 ns
addr_in <= "0010";
rw_in <= '0';
Z_inout <= "1100";
wait for 1 ns;
Z_inout <= "ZZZZ";
wait for 3 ns;

-- test 5: write when rw is high
-- expect: still 1011 at mem(0001)
-- time 4 ns, start 22 ns
addr_in <= "0001";
ce_in <= '0';
rw_in<= '1';
Z_inout <= "1101";
wait for 1 ns;
Z_inout <= "ZZZZ";
ce_in <= '1';
wait for 3 ns;

-- test 6: read when ce is high
-- expect: Z_inout is HHHH
-- time 4 ns, start 26 ns
addr_in <= "0000";
ce_in <= '1';
rw_in<= '1';
wait for 1 ns;
wait for 3 ns;

[rlindsberg]

@gitgnmn Can you confirm that tb for 1.4 works? The commit history shows that all sim passed expect assignment 1.4

[gitgnmn]

@rlindsberg will double check

[gitgnmn]

asserts in tb for 1.4 doesn't work as in all other tbs so far... but the rom works and simulation passed.

[rlindsberg]

asserts in tb for 1.4 doesn't work as in all other tbs so far... but the rom works and simulation passed.

Can you fix assert?

[gitgnmn]

asserts in tb for 1.4 doesn't work as in all other tbs so far... but the rom works and simulation passed.

Can you fix assert?

As all I've found what points to that I'm using it correctly and it doesn't feel like a very important thing to make work I might take a look at it later but not for this merger. I'll fork a branch from master specific for that purpose. When I do.

[rlindsberg]

So, looking at rw_memory the problem we had wasn't in rw_memory it self as much as in its test bench.

Not quite sure what you mean..

[rlindsberg]

@gitgnmn here you go.

[gitgnmn]

So, looking at rw_memory the problem we had wasn't in rw_memory it self as much as in its test bench.

Not quite sure what you mean..

If rw_memory:s simulation works as it is now the only difference between this code and the code we sat with yesterday is the absence of an else z_internal <= (others=>'Z') in the MEM_WRITE process and maybe that makes all the difference. But the difference in how the test benches look is much larger. I haven't tested if the old code would pas with the new test bench but I have a feeling it would. Or have you tried and know the answer already?

[rlindsberg]

So, looking at rw_memory the problem we had wasn't in rw_memory it self as much as in its test bench.

Not quite sure what you mean..

If rw_memory:s simulation works as it is now the only difference between this code and the code we sat with yesterday is the absence of an else z_internal <= (others=>'Z') in the MEM_WRITE process and maybe that makes all the difference. But the difference in how the test benches look is much larger. I haven't tested if the old code would pas with the new test bench but I have a feeling it would. Or have you tried and know the answer already?

I have tested your test bench with my tests, stilling failing.

[gitgnmn]

So, looking at rw_memory the problem we had wasn't in rw_memory it self as much as in its test bench.

Not quite sure what you mean..

If rw_memory:s simulation works as it is now the only difference between this code and the code we sat with yesterday is the absence of an else z_internal <= (others=>'Z') in the MEM_WRITE process and maybe that makes all the difference. But the difference in how the test benches look is much larger. I haven't tested if the old code would pas with the new test bench but I have a feeling it would. Or have you tried and know the answer already?

I have tested your test bench with my tests, stilling failing.

So, the solution was in the test bench then(?).

[rlindsberg]

You may absolutely test that if you've got time. I also feel sad to leave the old test bench without knowing why it didn't work.

[rlindsberg]

So, looking at rw_memory the problem we had wasn't in rw_memory it self as much as in its test bench.

Not quite sure what you mean..

If rw_memory:s simulation works as it is now the only difference between this code and the code we sat with yesterday is the absence of an else z_internal <= (others=>'Z') in the MEM_WRITE process and maybe that makes all the difference. But the difference in how the test benches look is much larger. I haven't tested if the old code would pas with the new test bench but I have a feeling it would. Or have you tried and know the answer already?

I have tested your test bench with my tests, stilling failing.

So, the solution was in the test bench then(?).

Yeah, mostly. Using TDD in this case helped me knowing what I was doing when writing code.

[gitgnmn]

You may absolutely test that if you've got time. I also feel sad to leave the old test bench without knowing why it didn't work.

Maybe another time. Let's merge this and continue with labb4 instead.