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rlindsberg / 1331IL-VHDL-Design

Microprocessor AR 4003
GNU General Public License v3.0
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Compile failed in Quartus; Error loading design in ModelSim #5

Closed rlindsberg closed 6 years ago

rlindsberg commented 6 years ago

https://github.com/rlindsberg/1331IL-VHDL-Design/blob/9486a7691ebf25ab2e86c60470e4a16806d4c9c7/alabb1/Carry_lookahead_adder/tb_b4_carry_lookahead_adder.vhd#L5-L12

screen shot 2018-09-04 at 13 48 34 2

rlindsberg commented 6 years ago

@gitgnmn Should I work on this or you have already written tb?

rlindsberg commented 6 years ago

So I'm working on this test bench

gitgnmn commented 6 years ago

You do that. I jumped straight to adder8 since you seemed to be so fast with the b4_ripple_adder, which should be done now.

rlindsberg commented 6 years ago

https://github.com/rlindsberg/1331IL-VHDL-Design/blob/7849f7496421799f6aa261e6525ace94c6ff0204/alabb1/Carry_lookahead_adder/b4_carry_lookahead_adder.vhd#L18-L44

b4_carry_lookahead_adder

@gitgnmn It seems that you have been outside and bicycling...

gitgnmn commented 6 years ago

It's from https://www.electronicshub.org/carry-look-ahead-adder/ but I guess that's a circuit "improved" for speed. I should have made the simpler one given as an example during the lecture. But I saw that one first after I had coded all that... spaghetti. If you want to change it for something more understandable than that's ok.

rlindsberg commented 6 years ago

Did you wrote the code based on this scheme?

gitgnmn commented 6 years ago

yes

rlindsberg commented 6 years ago

Wow! That's impressive!

rlindsberg commented 6 years ago

I used this one

rlindsberg commented 6 years ago

I ran a testbench of your code, without carry-in nor carry-out through. Here are the changes I made:

https://github.com/rlindsberg/1331IL-VHDL-Design/commit/97a0223f688aa940091d96a79adbe075e37eba2a#diff-ef474e5d4f5ccde22dec314f98130470R20

And here is the result:

screen shot 2018-09-04 at 20 16 23

rlindsberg commented 6 years ago

8+1 should give 1001, 15+3 should give 0010. But... 🙈🙈🙈

gitgnmn commented 6 years ago

So not totally unexpected, I most have forgotten/misstyped something. -.-

gitgnmn commented 6 years ago

Will you try to fix it or should I take a look at it tomorrow?

rlindsberg commented 6 years ago

Still good that I could get some value out of it! My testbench just gives me UUUUUUUU. It's too complicated to follow the data path of the component and actually hard code how the signals should move. Isn't it a structural model then?

rlindsberg commented 6 years ago

I'm rewriting it now. I will ask you for review when I finish. You can work on the README.md if you want :)

gitgnmn commented 6 years ago

"Isn't it a structural model then?" I'd think so concidering the detail level. It is quite literally describing the component on the gate level.

rlindsberg commented 6 years ago

Yes, but we're supposed to create a functional model 😅