search

rlindsberg / 1331IL-VHDL-Design

Microprocessor AR 4003
GNU General Public License v3.0
0 stars 0 forks source link

Functional 4 Bit CLA simulation passed #6

Closed rlindsberg closed 6 years ago

rlindsberg commented 6 years ago

closes #2 closes #5

Passed tests:

screen shot 2018-09-04 at 21 33 57

gitgnmn commented 6 years ago

Did you fix my code? I see you have a structural_b4_carry_lookahead_adder but I didn't see it mentioned in the test bed file.

rlindsberg commented 6 years ago

Did you fix my code?

I'm not smart enough to follow the data paths so I gave up after, like half an hour.

I see you have a structural_b4_carry_lookahead_adder but I didn't see it mentioned in the test bed file.

It's mentioned and used here: https://github.com/rlindsberg/1331IL-VHDL-Design/blob/72a32b612c0427d91a3033aafee83cf2923b1193/labb1/1.3/tb_structural_b4_carry_lookahead_adder.vhd#L11