Adder 8 not correct simulating result..

rlindsberg / 1331IL-VHDL-Design

Microprocessor AR 4003

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Closed rlindsberg closed 6 years ago

rlindsberg commented 6 years ago

Strange result: screen shot 2018-09-05 at 13 10 37

RTL scheme generated from Quartus is not the same as lab instruction: screen shot 2018-09-05 at 14 23 17