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rmadith / 554

Spring 2024 Capstone Project
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Make sure single-cycle processor passes HLL simulator randomized tests #15

Open thedubbers9 opened 5 months ago

thedubbers9 commented 5 months ago

4/4: Worked from 5:30-8PM, cleaned up output of python sim, successfully ran basic ADD instr in modelsim.

thedubbers9 commented 5 months ago

4/6-4/7 Worked from 9PM to 3:30AM. Refactored code, added pipeline registers. I am now running into an infinite loop when I attempt to execute the basic_jmp_test.hex file in the Verification folder.

thedubbers9 commented 5 months ago

4/8: @VishKing17 worked for about 6 hours debugging. Issue: RF bypass on single-cycle processor.

4/9: Worked from 1:30PM to 5:15PM. Implemented enumerated type and case inside statement to determine current instruction type given instruction binary. This is needed to display log trace in verilog testbench to compare against functional simulator