---
title: Wishbone vs. Furcula Bus
subtitle: Intel-style vs. Motorola-style Bus
How Wishbone Byte Lanes Work
|Lane |Byte 0|Byte 1|Byte 2|Byte 3|HWord 0|HWord 1|Word |
|:------------:|:----:|:----:|:----:|:----:|:-----:|:-----:|:---:|
|DAT\_IO[7:0] | X | | | | X | | X |
|DAT\_IO[15:8] | | X | | | X | | X |
|DAT\_IO[23:16]| | | X | | | X | X |
|DAT\_IO[31:24]| | | | X | | X | X |
Results in a slide which is garbled (copied from actual rendered page in web browser):
Wishbone vs. Furcula Bus
Intel-style vs. Motorola-style Bus
How Wishbone Byte Lanes Work
|Lane |Byte 0|Byte 1|Byte 2|Byte 3|HWord 0|HWord 1|Word | |:------------:|:----:|:----:|:----:|:----:|:-----:|:-----:|:---:| |DAT_IO[7:0] | X | | | | X | | X | |DAT_IO[15:8] | | X | | | X | | X | |DAT_IO[23:16]| | | X | | | X | X | |DAT_IO[31:24]| | | | X | | X | X |
Because of this, I must now render tables as images, which is inconvenient and somewhat wasteful. Is there any other work-around to this?
Example Markup used:
Results in a slide which is garbled (copied from actual rendered page in web browser):
Because of this, I must now render tables as images, which is inconvenient and somewhat wasteful. Is there any other work-around to this?