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robertdunne / FPGA-ARM

Verilog source code for book: Computer Architecture Tutorial
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Listing 15.5. Recursive subroutine factorial. Unexpected results #3

Closed chrisjhebert1973 closed 9 months ago

chrisjhebert1973 commented 9 months ago

Struggling with the recursive (stack based) factorial in listing 15.5. On DE10 Lite, this appears to never return from the call. Register R2 always only contains 0xc and other registers always appear to contain random data when running, so I'm assuming that it is somehow not returning from one of it's calls or overwriting it's stack somehow. I have a DE2-115 on order, I will try with this when it arrives.

The only difference between my setup and the setup in the book is that I have included and SDC file for timing analysis. Timing analysis is passing.

chrisjhebert1973 commented 9 months ago

Issue may have been related to my SDC file, Although there does still seem to be a huge setup slack for all corners with unconstrained paths. I will investigate this separately.