Two questions on your DMA FPGA hardware

[AnotherGitAccount]

Hello, I have two questions on your DMA FPGA hardware design.

1. Why did you chose 100MHz for the PLL output? It that the maximum for any of the used IPs?
2. How do you write to the ACP ID Mapper? Do you simply send data in its address space (which seems to start at 0x8000 0000 and end at 0xbfff ffff).

Edit (a third question):

Is the DMA mandatory to read and write to the ACP from the FPGA side (I dont need the HPS to see what's inside the OCR)?

Thanks!

[robertofem]

Hello:

1. I put 100MHz just for the example. 100MHz is a frequency that is fast and works for most implementations, that´s why. But you can force higher frequencies. The high you can go will depend on what else you put in the FPGA. Using the Quartus time analysis tools TimeQuest Analyzer you can check if you have paths with delays outside the safety. In these experiments from my thesis I reached 200MHz. I do not think you can go above that, even with an empty FPGA.
2. I do not remember quite well now what the ACP ID Mapper is but. I have two linux applications that use the hardware project you looking at:

• DMA_transfer_FPGA_DMAC: transfers from memory in the FPGA to On-Chip RAM in HPS. This does not uses ACP so I suppose you are not interested.
• DMA_transfer_FPGA_DMAC_driver: this transfers from FPGA memory to the cached memory through ACP. The memory allocation is done using the following driver: Alloc_DMAble_buff_LKM. This driver is needed because only from kernel space we can obtain the physical address of an allocated buffer, and we need this to tell the DMA controller in the FPGA, which works with physical addresses.

Hope you find the answer useful and thanks for whatching my code.

Regards!

[AnotherGitAccount]

Thanks for your answer! I'll dig into your driver example then :)