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robfinch / Cores

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GC interrupt enable register not writable by M-mode #4

Closed allenjbaum closed 4 years ago

allenjbaum commented 4 years ago

IF a CSR is accessible in some mode and is RW, then it is writable in that mode.

You are proposing a CSR which is accessible in all modes, but can be written (at least set) only by U-mode, which appears to be a spec violation ( and also a viirtualization hole, since it can be used to discover which mode the code is operating in

robfinch commented 4 years ago

I have switched the proposal so that the CSR may be updated by any mode.