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robfinch / Cores

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Example uart6551 use with 6502 #5

Open m1geo opened 1 week ago

m1geo commented 1 week ago

https://github.com/robfinch/Cores/blob/e5cffb9b83b6ec886261c2107d68bf825e193934/uart6551/trunk/rtl/uart6551.sv#L43C2-L43C56

Thanks for sharing your cores. I'm just wondering if you could share any more detail on how you interface the uart6551 design to a 6502 system.

I understand that the 8 LSBs connect to the data bus, and that sel_i has only address[0] while adr_i has address[3:2].

However it's unclear what some of the other wishbone connections (e.g., cyc_i, stb_i, etc.) should be tied to (for someone not familiar with the bus). A few lines in the documentation, or a simple diagram for the 8-bit nerds would be great.

Thanks :)

robfinch commented 6 days ago

Thanks, for your interest. I will add some detail to the docs. I would recommend reading up on the WISHBONE bus to get a better handle how to connect things. Details of the WISHBONE bus are bit outside of the scope of the core. While the core was meant mainly for system-on-chip I suppose it may be possible to connect to a 6502. I have not worked on the WISHBONE version for a couple of years. For system-on-chip I am using something called the FTA bus now, which is a bit more complex, and hopefully higher performance. FTA bus cannot be easily connected to a 6502.

m1geo commented 6 days ago

I have the UART up and running with a 6502 and sending data (albeit only 1 byte as once the FIFO full flag is set, I can't clear it (still debugging).

No problem on the Wishbone interface. I usually stick with AXI or an AMBA bus.

Thanks, the core has been useful!