Open robinsonb5 opened 10 years ago
Having proved with the TG68_MiniSOC project that the CPU core can be clocked slower than but in sync with SDRAM, solving the stability issues, need to apply this to the minimig core.
Having proved with the TG68_MiniSOC project that the CPU core can be clocked slower than but in sync with SDRAM, solving the stability issues, need to apply this to the minimig core.