Closed robinsonb5 closed 12 years ago
My current working theory is that this is caused by long combinatorial chains in the core on the main CPU's address lines, resulting in the SDRAM controller latching the values before they're stable. Delaying the main CPU's ramcs signal by a cycle or two seems to help a great deal.
Tentatively closing, since I haven't had a bad build since adding the extra wait state.
The core suffers from build-to-build stability problems, which usually manifest as problems wtih the TG68 core when fast RAM is enabled.
Adding or removing unrelated features to the core, or fiddling with compilation settings can fix it. A marginal build can work fine on one Chameleon and fail on another.