Need advice please D1H

[ylyamin]

Hi,

I am very impressive of your work to manage bare-metal Allwinner T113. As is documentation very limited regarding peripherals it's amazing how you were able to write such laconic code. Sorry that I ask it in issue, just I don't know how to contact you.

Actually I want to do the same, but with Allwinner D1H, believe is chip with identical peripheral as T113 but with RISC-V core. I used RT-Thread OS and manage to run LCD MIPI DSI display with D1H.

But with USB I'm completely stuck, maybe you could give me some advice please? I would be very appreciated.

This is my repository and several articles about changes

I try to do the same as in your project:

1. Deactivate EHCI:

rt-thread/bsp/allwinner/d1s_d1h/packages/TinyUSB/rt-thread/bsp/sunxi_D1/drv_tinyusb.c

    volatile uint32_t *usb_ctrl = (uint32_t * ) (EHCI1_BASE + 0x800); //HCI interface
    volatile uint32_t *phy_ctrl = (uint32_t * ) (EHCI1_BASE + 0x810); //PHY cntrl
    volatile uint32_t *portsc  = (uint32_t * ) (EHCI1_BASE + 0x054);  //E_PORTSC
    *phy_ctrl &= ~BV(3);
    *usb_ctrl |= BV(10) | BV(9) | BV(8) | BV(0);
    *portsc |= BV(13);

2. Add few places to clear/invalidate caches, in rt-thread/bsp/allwinner/d1s_d1h/packages/TinyUSB/src/portable/ohci/ohci.c:

   static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes)
   {
   ...
   rt_hw_cpu_dcache_clean_and_invalidate_local(data_ptr, total_bytes);
   }

3. Define DMA memory section:

rt-thread/bsp/allwinner/d1s_d1h/link.lds

MEMORY
{
    SRAM : ORIGIN = 0x40300000, LENGTH = 4M
    DMA :  ORIGIN = 0x40700000, LENGTH = 16M
    HEAP : ORIGIN = 0x41700000, LENGTH = 16M
}

SECTIONS
{
    .usb :
    {
        . = ALIGN(4);   
    } > DMA

Init MMU with different sections in rt-thread/bsp/allwinner/d1s_d1h/board/board.c:

struct mem_desc platform_mem_desc[] = {
    {KERNEL_VADDR_START, 0x40700000 - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM},       //KERNEL
    {0x1000, 0x3ffff000 - 1, (rt_size_t)ARCH_MAP_FAILED, DEVICE_MEM},                   //IO
    {0x40700000, 0x40700000 + 0x1000000 - 1, (rt_size_t)ARCH_MAP_FAILED, DEVICE_MEM},   //DMA
    {0x41700000, 0x40700000 + 0x4000000 - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM},   //HEAP + HW PAGE
};

rt-thread/bsp/allwinner/d1s_d1h/packages/TinyUSB/src/portable/ohci/ohci.c

CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static ohci_data_t ohci_data;

Run board.

Looks like USB device start to do something new, but all data transfers did not produce any results, all of it STALLED or FAULT:

[0:0] Open EP0 with Size = 8
Get 8 byte of Device Descriptor
[0:0] Get Descriptor: 80 06 00 01 00 00 08 00
on EP 00 with 8 bytes
on EP 80 with 8 bytes
[0:0] Control STALLED, xferred_bytes = 8

[0:0] Get Descriptor: 80 06 00 03 D0 03 08 00 
on EP 00 with 8 bytes
on EP 80 with 8 bytes
[0:0] Control STALLED, xferred_bytes = 8

[0:0] Get Descriptor: 80 06 00 02 18 08 08 00 
on EP 00 with 8 bytes
on EP 80 with 8 bytes
[0:0] Control STALLED, xferred_bytes = 8

[0:0] Get Descriptor: 80 06 00 02 58 0C 08 00 
on EP 00 with 8 bytes
on EP 00 with 4294964828 bytes

Set Address = 1
[0:0] Set Address: 00 05 01 00 00 00 00 00
on EP 00 with 0 bytes
[0:0] Control STALLED, xferred_bytes = 0

[0:0] Set Address: 00 05 01 02 00 00 00 00 
on EP 00 with 0 bytes
on EP 00 with 2088 bytes

[0:0] Get Descriptor: 80 06 00 01 00 00 12 00 
on EP 00 with 8 bytes
[0:1] Control FAILED, xferred_bytes = 8

Looks like communication not working.

[robots]

There are 2 places where to Invalidate / clean cache.

• First place is when you are writing memory for DMA to transfer. This is Clear.
• second is when you receive data using DMA. You need to invaldate cache, to reread the content of memory.

First is done in ohci.c driver, second is done in hid_host.c (lib/tinyusb-ohci/src/class/hid/hid_host.c)

Its very tricky to do. Second possibility is to make the DMA memory non cachable, but it didnt work for me. Also i tried to make in clean to invalidate cache inside Ohci.c after receiving data but i failed. Thats why it is in hid_host.c

(BTW D1 and T113 are the same silicon, all peripherals are exactly the same, so code for T113 should run on D1 (except for the cpu related stuff))

[ylyamin]

Hi @robots ,

Thank you very much for your reply and support. Tried to add an invalidate cache in hid_host.c: nothing changed, still not work.

Didn't know if maybe is RT-Thread OS specific. Something is wrong with MMU init or compiler version, also RTT use OpenSBI. No idea.

Looks like I need to start from barebone with your code and RISC-V.