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robseb / HPS2FPGAmapping

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
MIT License
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DTS related question #1

Open filip-dahlberg opened 3 years ago

filip-dahlberg commented 3 years ago

Hi Seb,

Thanks for all the great work you've done. I'm wondering about the device tree source file that you've written. The FPGA configuration that I'm using will not enable some of the peripherals in Platform Designer, as you've enabled for the DE0-NANO. Will Linux crash if this is the case, that your dts file contains support for peripherals that the Platform Designer app has not enabled in my FPGA project?

Will I have to edit your device three source file? Or can I inherit it as it is? I'm using EMAC1 (HPSI/O Set 0), SD/MMC (HPS I/O set 0, 4-bit data), and I2C0 (HPS I/O Set 1). The above noted peripherals I've enabled in Platform Designer. Also, I've configured the AXI Bridges as you guide in this repo describes.

All the best

robseb commented 3 years ago

The Linux will only crash in case it tries to access non-accessible addresses. I enbaled whithin my Linux Distro the Kernal Debug Mesages. The Kernel will show in case a driver is not loadebile a Error Msg. This will be the case if the Linux tries to load a driver that was not enabable inside Quartus Prime Platform Designer. Based of a bug in SoC EDS 18.1 I had this isssue during developing often.

filip-dahlberg commented 3 years ago

Thanks for your reply. Then it seems like the Kernel will output error messages, however this will not result in Linux crash as long as the drivers are not accessing non-accessible addresses. I can then proceed with using your DTS file. Many thanks robseb.

robseb commented 3 years ago

Yes, you can also follow my rsyocto guide to create a own version. This guide here is a older version with EDS 18.1. The Quartus Prime FPGA side is vailed until today. The Linux side chnagned.

filip-dahlberg commented 3 years ago

Ok cool. My intention is to use the DTS file from rsyocto release 1.041, located inside folder for DE0 Nano platform. Then I've followed the guide in https://github.com/robseb/meta-intelfpga for building the Yocto powered Linux distribution. Then I'll intend to apply the rs-tools layer to leverage HPS-FPGA comms. Then I'll try to but it all together with https://github.com/robseb/socfpgaPlatformGenerator for generating the SD card image.