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robseb / LinuxVSCppFPGA

C++ examples for accessing FPGA Soft-IP and Hard-IP with embedded Linux for Intel (ALTERA) SoC-FPGAs (Cyclone V)
MIT License
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MSEL settings #3

Closed rokzitko closed 2 years ago

rokzitko commented 2 years ago

In guide 1 on booting, there is an inconsistency between the text and the picture regarding the MSEL settings. The picture shows 0b00100, while the text says 0b00101. I believe 0b00100 (picture) is correct.

robseb commented 2 years ago

Hello @rokzitko, Your problems relate to the primary project robseb / rsyocto. You are right, the MSEL switch configuration for the Cyclone V is different in the picture than the text. The configuration of the text enables the compression of the FPGA configuration file. This is not used by my bootloader. The FPGA configuration cannot be written (all FPGAs LEDs are off) and the bridges are ready. Use the MSEL configuration from 0b00100 and check that the FPGAs LEDs are lit on. Thank you for the report, I will change the picture in the next publication. Robin