Closed robstave closed 3 months ago
/**
// ATTiny overview // +-\/-+ // Reset 1| |8 VCC // (pin3) OUT2 PB3 2| |7 PB2 (pin2/int0) CLOCK // (pin4) OUT3 PB4 3| |6 PB1 OUT2 (pin1) s0 // GND 4| |5 PB0 OUT0 (pin0) out // ------
const int int0 = 0; // interrupt 0
volatile byte pattern; int patternCount = 0;
boolean pattern_0[PATTERN_0_SIZE] = { HIGH, HIGH, LOW, LOW, LOW, LOW, LOW, LOW };
boolean pattern_1[PATTERN_0_SIZE] = { LOW, LOW, HIGH, HIGH, LOW, LOW, LOW, LOW };
boolean pattern_2[PATTERN_0_SIZE] = { LOW, LOW, LOW, LOW, HIGH, HIGH, LOW, LOW };
boolean pattern_3[PATTERN_0_SIZE] = { LOW, LOW, LOW, LOW, LOW, LOW, HIGH, HIGH };
volatile byte counter0 = 0; volatile byte counter1 = 0; volatile byte counter2 = 0; volatile byte counter3 = 0;
void setup() {
PORTB = 0x00; //enable all pull-down
DDRB = B00011011; // set PORTB to inputs except PB0
attachInterrupt(int0, clockCounter, CHANGE); // clockInt is our interrupt, clockCounter function is called when // invoked on either clock edge } boolean setPatternValue() { boolean result = LOW;
result = pattern_0[counter0];
if (result == HIGH) {
PORTB |= _BV(PB0);
} else { PORTB &= ~_BV(PB0); }
counter0++; if (counter0 >= PATTERN_0_SIZE) { counter0 = 0; }
result = pattern_1[counter1];
if (result == HIGH) {
PORTB |= _BV(PB1);
} else { PORTB &= ~_BV(PB1); }
counter1++; if (counter1 >= PATTERN_1_SIZE) { counter1 = 0; }
result = pattern_2[counter2];
if (result == HIGH) {
PORTB |= _BV(PB3);
} else { PORTB &= ~_BV(PB3); }
counter2++; if (counter2 >= PATTERN_2_SIZE) { counter2 = 0; }
result = pattern_3[counter3];
if (result == HIGH) {
PORTB |= _BV(PB4);
} else { PORTB &= ~_BV(PB4); }
counter3++; if (counter3 >= PATTERN_3_SIZE) { counter3 = 0; } }
/**
void loop() { // loop d loop }
0610
speed in four outputs, but the phase is 90 degrees
so
internally, there will be a switch that can do gate/trigger I guess