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romancardenas / riscv-slic

Crate for enabling vectored handling of software interrupts for RISC-V targets
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Support RP2350 #9

Open thejpster opened 2 months ago

thejpster commented 2 months ago

The Raspberry Pi RP2350's Hazard3 RISC-V code includes the Xh3irq interrupt controller, which automatically works out which interrupt should be handled next according to their priorities and pending states.

I wrote a driver for it in this PR: https://github.com/rp-rs/rp-hal/pull/847.

Perhaps we could support the RP2350 here, using that.

romancardenas commented 2 months ago

Thanks for opening the issue! Does this target have a MachineSoft interrupt source? I did a very quick check and only found references to MachineExternal.

thejpster commented 2 months ago

https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#reg-rvcsr-MIE

You can you turn it on. Haven't tried it.

romancardenas commented 2 months ago

Will take a look and see how it works. Sounds like it is feasible to support this target 😁

romancardenas commented 2 months ago

Looks like we can use the RISCV_SOFTIRQ register of the SIO module:

Screenshot 2024-09-04 at 10 04 25
thejpster commented 2 months ago

That sounds like it lets you set SIP on the other core or the current core. I suspect there is also a CSR which only lets you set SIP on the current core.

romancardenas commented 2 months ago

Please take a look at this PR, maybe it is enough for RP2350 😀

I still want to do more tests etc., but it is potentially an all-in-one solution