vmayoral
commented
3 years ago @jasvinderkhurana, colcon acceleration hls simple_adder --run is either not running it, or dumping an error, which is why you see things as Not Run. Review logs files under build-kv260 to understand the cause, or use the --verbose flag to get it in stdout.
jasvinder@jasvinder-ubuntu:~/krs_ws$ colcon acceleration hls simple_adder --synthesis-report Project: project_simpleadder1 Path: /home/jasvinder/krs_ws/build-kv260/simple_adder/project_simpleadder1 - Solution: solution_4ns - C Simulation: Not Run - C Synthesis: Not Run - C/RTL Co-simulation: Not Run - Export: - IP Catalog: Not Run - System Generator: Not Run - Export Evaluation: Not Run - Synthesis report: /home/jasvinder/krs_ws/build-kv260/simple_adder/project_simpleadder1/solution_4ns/syn/report/simple_adder_csynth.rpt [0.537s] ERROR:colcon:colcon acceleration: [Errno 2] No such file or directory: '/home/jasvinder/krs_ws/build-kv260/simple_adder/project_simpleadder1/solution_4ns/syn/report/simple_adder_csynth.rpt' Traceback (most recent call last): File "/usr/lib/python3/dist-packages/colcon_core/command.py", line 528, in verb_main rc = context.args.main(context=context) File "/home/jasvinder/krs_ws/install/lib/python3.8/site-packages/colcon_acceleration/subverb/hls.py", line 495, in main self.print_status_solution(s, configuration, context) File "/home/jasvinder/krs_ws/install/lib/python3.8/site-packages/colcon_acceleration/subverb/hls.py", line 273, in print_status_solution with open(csyn_path,'r') as f: FileNotFoundError: [Errno 2] No such file or directory: '/home/jasvinder/krs_ws/build-kv260/simple_adder/project_simpleadder1/solution_4ns/syn/report/simple_adder_csynth.rpt'
These errors appear because you're asking for the report (--synthesis-report) when it has not run successfully just yet (there's no report to open). We should probably consider this and manage exception differently.
I reproduced it and it works perfectly fine for me. Here's my output. Note I'm using the --verbose to inspect the build process:
```bash
xilinx@xilinx:~/ros2_ws$ colcon acceleration hls simple_adder
Project: project_simpleadder2
Path: /home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder2
- Solution: solution_4ns
- C Simulation: Not Run
- C Synthesis: Not Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Not Run
- System Generator: Not Run
- Export Evaluation: Not Run
- Solution: solution_10ns
- C Simulation: Not Run
- C Synthesis: Not Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Not Run
- System Generator: Not Run
- Export Evaluation: Not Run
Project: project_simpleadder1
Path: /home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder1
- Solution: solution_4ns
- C Simulation: Not Run
- C Synthesis: Not Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Not Run
- System Generator: Not Run
- Export Evaluation: Not Run
xilinx@xilinx:~/ros2_ws$
xilinx@xilinx:~/ros2_ws$
xilinx@xilinx:~/ros2_ws$ colcon acceleration hls simple_adder --run --verbose
Found Tcl script "project_simpleadder2.tcl" for package: simple_adder
Executing /home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder2.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2.2 (64-bit)
**** SW Build 3118627 on Tue Feb 9 05:13:49 MST 2021
**** IP Build 3115676 on Tue Feb 9 10:48:11 MST 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'xilinx' on host 'xilinx' (Linux_x86_64 version 5.11.0-27-generic) on Mon Aug 30 20:42:38 CEST 2021
INFO: [HLS 200-10] On os Ubuntu 20.04.2 LTS
INFO: [HLS 200-10] In directory '/home/xilinx/ros2_ws/build-kv260/simple_adder'
Sourcing Tcl script '/home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder2.tcl'
INFO: [HLS 200-1510] Running: open_project -reset project_simpleadder2
INFO: [HLS 200-10] Creating and opening project '/home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder2'.
INFO: [HLS 200-1510] Running: add_files /home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/adder2.cpp
INFO: [HLS 200-10] Adding design file '/home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/adder2.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb /home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/testbench2.cpp -cflags -I /home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/include -I /home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/include
INFO: [HLS 200-10] Adding test bench file '/home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/testbench2.cpp' to the project
INFO: [HLS 200-1510] Running: set_top simple_adder
INFO: [HLS 200-1510] Running: open_solution -flow_target vitis solution_4ns
INFO: [HLS 200-10] Creating and opening solution '/home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder2/solution_4ns'.
INFO: [HLS 200-1505] Using flow_target 'vitis'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_latency=64
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_alignment_byte_size=64
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_max_widen_bitwidth=512
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_offset=slave
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_rtl -register_reset_num=3
INFO: [HLS 200-1510] Running: set_part xck26-sfvc784-2lv-c
INFO: [HLS 200-10] Setting target device to 'xck26-sfvc784-2LV-c'
INFO: [HLS 200-1510] Running: create_clock -period 4
INFO: [SYN 201-201] Setting up clock 'default' with a period of 4ns.
INFO: [HLS 200-1510] Running: csim_design -ldflags -lOpenCL -profile
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch CLANG as the compiler.
Compiling ../../../../../../src/xilinx/acceleration_examples/simple_adder/src/testbench2.cpp in debug mode
Compiling ../../../../../../src/xilinx/acceleration_examples/simple_adder/src/adder2.cpp in debug mode
Generating csim.exe
Expected result: 10000, Got Result: 10000
Expected result: 10405, Got Result: 10405
Expected result: 10824, Got Result: 10824
Expected result: 11263, Got Result: 11263
Expected result: 11728, Got Result: 11728
Expected result: 12225, Got Result: 12225
Expected result: 12760, Got Result: 12760
Expected result: 13339, Got Result: 13339
Expected result: 13968, Got Result: 13968
Expected result: 14653, Got Result: 14653
Generating dot files
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.91 seconds. CPU system time: 0.4 seconds. Elapsed time: 1.1 seconds; current allocated memory: 211.166 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 211.358 MB.
INFO: [HLS 200-10] Analyzing design file '/home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/adder2.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.14 seconds. CPU system time: 0.15 seconds. Elapsed time: 0.35 seconds; current allocated memory: 212.039 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vitis' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 2.69 seconds. CPU system time: 0.26 seconds. Elapsed time: 2.96 seconds; current allocated memory: 212.424 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 212.426 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 213.392 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 212.827 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 232.885 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 224.581 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'simple_adder' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'simple_adder'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.02 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 224.816 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 224.965 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'simple_adder'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'simple_adder/a' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'simple_adder/b' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'simple_adder' to 's_axilite & ap_ctrl_chain'.
INFO: [RTGEN 206-100] Bundling port 'return' and 'b' to AXI-Lite port control.
INFO: [RTGEN 206-100] Generating core module 'mul_32s_32s_32_2_1': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'simple_adder'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 225.296 MB.
INFO: [RTMG 210-282] Generating pipelined core: 'simple_adder_mul_32s_32s_32_2_1_Multiplier_0'
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 1.03 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.06 seconds; current allocated memory: 233.071 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for simple_adder.
INFO: [VLOG 209-307] Generating Verilog RTL for simple_adder.
INFO: [HLS 200-789] **** Estimated Fmax: 422.83 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4.15 seconds. CPU system time: 0.45 seconds. Elapsed time: 4.73 seconds; current allocated memory: 233.301 MB.
INFO: [HLS 200-1510] Running: open_solution -flow_target vitis solution_10ns
INFO: [HLS 200-10] Creating and opening solution '/home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder2/solution_10ns'.
INFO: [HLS 200-1505] Using flow_target 'vitis'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_latency=64
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_alignment_byte_size=64
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_max_widen_bitwidth=512
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_offset=slave
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_rtl -register_reset_num=3
INFO: [HLS 200-1510] Running: set_part xck26-sfvc784-2lv-c
INFO: [HLS 200-1510] Running: create_clock -period 10
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1510] Running: csim_design -ldflags -lOpenCL -profile
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch CLANG as the compiler.
Compiling ../../../../../../src/xilinx/acceleration_examples/simple_adder/src/testbench2.cpp in debug mode
Compiling ../../../../../../src/xilinx/acceleration_examples/simple_adder/src/adder2.cpp in debug mode
Generating csim.exe
Expected result: 10000, Got Result: 10000
Expected result: 10405, Got Result: 10405
Expected result: 10824, Got Result: 10824
Expected result: 11263, Got Result: 11263
Expected result: 11728, Got Result: 11728
Expected result: 12225, Got Result: 12225
Expected result: 12760, Got Result: 12760
Expected result: 13339, Got Result: 13339
Expected result: 13968, Got Result: 13968
Expected result: 14653, Got Result: 14653
Generating dot files
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.53 seconds. CPU system time: 0.24 seconds. Elapsed time: 0.77 seconds; current allocated memory: 221.840 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 221.886 MB.
INFO: [HLS 200-10] Analyzing design file '/home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/adder2.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.13 seconds. CPU system time: 0.12 seconds. Elapsed time: 0.27 seconds; current allocated memory: 221.955 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vitis' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 2.68 seconds. CPU system time: 0.24 seconds. Elapsed time: 2.92 seconds; current allocated memory: 222.029 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 222.030 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 222.757 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 222.164 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 242.145 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 233.800 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'simple_adder' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'simple_adder'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.01 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.03 seconds; current allocated memory: 233.864 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 233.989 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'simple_adder'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'simple_adder/a' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'simple_adder/b' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'simple_adder' to 's_axilite & ap_ctrl_chain'.
INFO: [RTGEN 206-100] Bundling port 'return' and 'b' to AXI-Lite port control.
INFO: [RTGEN 206-100] Generating core module 'mul_32s_32s_32_1_1': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'simple_adder'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 234.203 MB.
INFO: [RTMG 210-282] Generating pipelined core: 'simple_adder_mul_32s_32s_32_1_1_Multiplier_0'
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.97 seconds. CPU system time: 0.03 seconds. Elapsed time: 1 seconds; current allocated memory: 235.591 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for simple_adder.
INFO: [VLOG 209-307] Generating Verilog RTL for simple_adder.
INFO: [HLS 200-789] **** Estimated Fmax: 183.96 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4.08 seconds. CPU system time: 0.4 seconds. Elapsed time: 4.5 seconds; current allocated memory: 235.739 MB.
INFO: [HLS 200-112] Total CPU user time: 11.87 seconds. Total CPU system time: 2.02 seconds. Total elapsed time: 12.98 seconds; peak allocated memory: 242.145 MB.
INFO: [Common 17-206] Exiting vitis_hls at Mon Aug 30 20:42:51 2021...
Found Tcl script "project_simpleadder1.tcl" for package: simple_adder
Executing /home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder1.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2.2 (64-bit)
**** SW Build 3118627 on Tue Feb 9 05:13:49 MST 2021
**** IP Build 3115676 on Tue Feb 9 10:48:11 MST 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'xilinx' on host 'xilinx' (Linux_x86_64 version 5.11.0-27-generic) on Mon Aug 30 20:42:52 CEST 2021
INFO: [HLS 200-10] On os Ubuntu 20.04.2 LTS
INFO: [HLS 200-10] In directory '/home/xilinx/ros2_ws/build-kv260/simple_adder'
Sourcing Tcl script '/home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder1.tcl'
INFO: [HLS 200-1510] Running: open_project -reset project_simpleadder1
INFO: [HLS 200-10] Creating and opening project '/home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder1'.
INFO: [HLS 200-1510] Running: add_files /home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/adder1.cpp
INFO: [HLS 200-10] Adding design file '/home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/adder1.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb /home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/testbench1.cpp -cflags -I /home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/include
INFO: [HLS 200-10] Adding test bench file '/home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/testbench1.cpp' to the project
INFO: [HLS 200-1510] Running: set_top simple_adder
INFO: [HLS 200-1510] Running: open_solution -flow_target vitis solution_4ns
INFO: [HLS 200-10] Creating and opening solution '/home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder1/solution_4ns'.
INFO: [HLS 200-1505] Using flow_target 'vitis'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_latency=64
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_alignment_byte_size=64
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_max_widen_bitwidth=512
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_interface -m_axi_offset=slave
INFO: [HLS 200-435] Setting 'open_solution -flow_target vitis' configuration: config_rtl -register_reset_num=3
INFO: [HLS 200-1510] Running: set_part xck26-sfvc784-2lv-c
INFO: [HLS 200-10] Setting target device to 'xck26-sfvc784-2LV-c'
INFO: [HLS 200-1510] Running: create_clock -period 4
INFO: [SYN 201-201] Setting up clock 'default' with a period of 4ns.
INFO: [HLS 200-1510] Running: csim_design -ldflags -lOpenCL -profile
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch CLANG as the compiler.
Compiling ../../../../../../src/xilinx/acceleration_examples/simple_adder/src/testbench1.cpp in debug mode
Compiling ../../../../../../src/xilinx/acceleration_examples/simple_adder/src/adder1.cpp in debug mode
Generating csim.exe
Expected result: 100, Got Result: 100
Expected result: 103, Got Result: 103
Expected result: 106, Got Result: 106
Expected result: 109, Got Result: 109
Expected result: 112, Got Result: 112
Expected result: 115, Got Result: 115
Expected result: 118, Got Result: 118
Expected result: 121, Got Result: 121
Expected result: 124, Got Result: 124
Expected result: 127, Got Result: 127
Generating dot files
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.81 seconds. CPU system time: 0.33 seconds. Elapsed time: 0.82 seconds; current allocated memory: 195.117 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 195.341 MB.
INFO: [HLS 200-10] Analyzing design file '/home/xilinx/ros2_ws/src/xilinx/acceleration_examples/simple_adder/src/adder1.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.14 seconds. CPU system time: 0.13 seconds. Elapsed time: 0.26 seconds; current allocated memory: 196.006 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vitis' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 2.64 seconds. CPU system time: 0.27 seconds. Elapsed time: 2.92 seconds; current allocated memory: 196.391 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 196.393 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.02 seconds; current allocated memory: 197.356 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 196.792 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 216.844 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 208.545 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'simple_adder' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'simple_adder'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 208.744 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 208.871 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'simple_adder'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'simple_adder/a' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'simple_adder/b' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'simple_adder' to 's_axilite & ap_ctrl_chain'.
INFO: [RTGEN 206-100] Bundling port 'return' and 'b' to AXI-Lite port control.
INFO: [RTGEN 206-100] Finished creating RTL model for 'simple_adder'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 209.110 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.91 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.92 seconds; current allocated memory: 216.446 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for simple_adder.
INFO: [VLOG 209-307] Generating Verilog RTL for simple_adder.
INFO: [HLS 200-789] **** Estimated Fmax: 496.03 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 3.93 seconds. CPU system time: 0.42 seconds. Elapsed time: 4.36 seconds; current allocated memory: 216.647 MB.
INFO: [HLS 200-112] Total CPU user time: 6.79 seconds. Total CPU system time: 1.14 seconds. Total elapsed time: 6.66 seconds; peak allocated memory: 216.844 MB.
INFO: [Common 17-206] Exiting vitis_hls at Mon Aug 30 20:42:59 2021...
Project: project_simpleadder2
Path: /home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder2
- Solution: solution_4ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Not Run
- System Generator: Not Run
- Export Evaluation: Not Run
- Solution: solution_10ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Not Run
- System Generator: Not Run
- Export Evaluation: Not Run
Project: project_simpleadder1
Path: /home/xilinx/ros2_ws/build-kv260/simple_adder/project_simpleadder1
- Solution: solution_4ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Not Run
- System Generator: Not Run
- Export Evaluation: Not Run
```
Try the --verbose flag or review the logs. We need to know what's wrong in your system to diagnose why HLS is not running CSIM.
jasvinderkhurana
I am trying to get synthesis report for simple_adder accelerator, but it is not executing C Simulation. Please see logs below
Please guide for possible issue.