Sainsmart DDS120 support

[merbanan]

Hi, I have a Sainsmart device and I am trying to get it working. So far your firmware seems to be running correctly with the exception of not outputting any valid samples (I modified the sigrok version slightly). http://sigrok.org/wiki/File:DDS120_Top_20141024_0540p.jpg is a picture of the pcb. Do you have any idea what could be the magic that is needed for working sampling? Long shot but I'd rather not go through all the asm code.

[jhoenicke]

It looks like you got it working: http://www.eevblog.com/forum/testgear/sainsmart-dds120-usb-oscilloscope-(buudai-bm102)/325/

I still have to try the sigrok code. Is the isochronous transfer mode working for that? Although bulk transfer allows 30 MB/s, you get a fifo overrun from time to time, which leads to lost samples. With isochronous you should be able to get a very stable transfer at 24 MB/s. BTW, 48 Megasamples/s cannot work since USB 2 is not fast enough to allow continuous sampling and the EZ-USB can just use 2kb of it's 4kb buffer in bulk mode.

[merbanan]

Well I am able to load it and talk to it, but I had trouble getting samples out.

But now with some more testing it seems that the adc is only clocked when I am using the 30MHz and 48MHz. Do you have any idea what that means ?

[jhoenicke]

the 6022be uses the IFCLK pin in 30/48 MHz mode and the CTL2 pin in low speed mode. Probably the SainSmart doesn't use the CTL2 pin. You may want to check if there is another output pin of the ez-usb connected to the IFCLK pin.

If not, you can always clock the ADC with the full 48 Mhz (0xea in ifcfg) and set out0 (currently 0x40) and the two 0x44 bytes afterwards to 0x00 (in set_samplerate). This is probably not the most efficient way to run the ADC though.

To use another pin you would need to shift the 0x40 / 0x44 for out0. E.g. 0x20/0x22 for ctl1, 0x10/0x11 for ctl0.

[merbanan]

The Sainsmart can only do 240kHz, 2.4MHz and "50MHz" (I guess it is 48MHz). To me that suggest that only IFCLK is connected. What rates would be possible to get in that case ?

[merbanan]

It seems the fx2lafw only uses IFCLK at 48MHz or 30MHz and is able to set different sample rates via GPIF. Have you investigated the method that code uses for that ? I will most likely need to use that kind of code to get the Sainsmart in working order.

[jhoenicke]

The 6200be also uses the GPIF waveform generator. The code is in set_samplerate. If you have the right waveform data you can just copy it or you can try to understand it. The waveform for the 6200be is quite simple: take a sample, output low on CTL2, wait n cycles, then output high on CTL2 wait n-1 cycles, then go back to the beggining (1 cycle). So it is the CTL2 pin that drives the ADC in this mode. If the Sainsmart uses a different output pin, you need to adapt the program as I tried to explain above.

[merbanan]

The Sainsmart ADC is connected to IFCLK directly, so the ADC can only be run at 30MHz or 48MHz. Per my understanding it should be possible to fill the FIFO at an even divisor from those base clocks. But I don't know how to do that yet.

[jhoenicke]

After looking at the image, I see that no CTL pin is connected. Have you tried changing ifcfg to 0xea from 0xca in set_samplerate for all modes (except 30 MHz) and leaving the rest unchanged? This should clock the ADC with 48 MHz, while only polling the data at the lower frequencies.

[merbanan]

With your hints I got it working. Did you ever plan to add a few more sample frequencies ? If I understand everything correctly it should be possible to get 15, 12 and 10MHz (and a few more). Did you just not bother or is there something that limits that possibility?

[jhoenicke]

I support 12 MHz since it is the maximum you can use with two channels and isochronous transfer (24 MB/s). I thought 15 is too close to 16 and 10 to close to 12 and 8 to be useful. But there is no reason why you shouldn't be able to support 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16, 24, 30 MHz and a few fractional rates like 7.5 or 9.6 MHz.

BTW, you should probably change out0 and the two occurences of 0x44 to 0 in set_samplerate. These are used to drive the CTL2 pin which you don't need. It doesn't really matter since they are not connected. But if someone installs the firmware accidently on the Hantek, it may damage the chip since IFCLK and CTL2 are connected there.

[merbanan]

Can you post a diff how it should be done? I am fairly sure how to do it but code would make it crystal clear.

And I'll try to figure out how to enable those rates you listed. I just think that the firmware should enable everything the hardware can. If someone uses it or not shouldn't be up to the firmware. One more question, what is the slowest sample rate possible? I can see a use for really slow rates. For example measuring stuff over several days.

[jhoenicke]

Here is a diff (untested): https://gist.github.com/jhoenicke/8cee95a29bdee66d7e6b00869b92caa1

Minimum rate: 100 kHz is close to minimum with this method. If you use all seven slots of the GPIF you can delay 6x256 cycles and get 20 kHz sampling rate. In principle you may even use some timer interrupt in connection with a singleshot GPIF program to get arbitrary slow sample rates. I'm not sure how to do this, though. It is probably easier to record with 100 kHz and do post-processing of the samples on the PC side.

Note that for the lower sample rates a lot of intermediate rates are possible. Do you really want to support 123.45679 kHz?

[merbanan]

I'll think the best way is as you say to do post-processing on the 100kHz data if you need lower sample rates. And I think adding 5 more high sample rates will be enough for most use cases.

When I started looking though all the sample rates I found 6MHz and 2MHz. Both can be derived from both 48 and 30 MHz clock. What base clock should they use for best sample stability ?