rsnikhil / Forvis_RISCV-ISA-Spec

Formal specification of RISC-V Instruction Set
MIT License
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Question: configuration / compilation settings for RV32 #5

Open ghost opened 6 years ago

ghost commented 6 years ago

hello,

I tried to simulate a few toy programs with forvis aka RISCV-ISA-Spec-exe. But up to now, it did not succeed. Are there any specific configuration settings, or compilation settings to know?

Thank you,

I am using riscv-gcc for RV32-IM cores:

$ riscv32-unknown-elf-gcc -v
Using built-in specs.
COLLECT_GCC=riscv32-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/riscv/libexec/gcc/riscv32-unknown-elf/7.2.0/lto-wrapper
Target: riscv32-unknown-elf
Configured with: /src/riscv-gnu-toolchain/build/../riscv-gcc/configure --target=riscv32-unknown-elf --prefix=/riscv --disable-shared --disable-threads --enable-languages=c,c++ --with-system-zlib --enable-tls --with-newlib --with-sysroot=/riscv/riscv32-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --src=../../riscv-gcc --enable-checking=yes --disable-multilib --with-abi=ilp32 --with-arch=rv32im 'CFLAGS_FOR_TARGET=-Os  -mcmodel=medlow'
Thread model: single
gcc version 7.2.0 (GCC) 

A simple test program to start with:

$ cat hello.c
#include <stdio.h>
 int main(void) { printf("Hello world!\n"); return 0; }
$ riscv32-unknown-elf-gcc hello.c -o hello.elf

Simulation test:

$ stack exec forvis -- --RV32 --tohost -v1 Test_Programs/boot_ROM_RV32.hex32 hello.elf 
Type -h, -H or --help for help.
Input file: Test_Programs/boot_ROM_RV32.hex32
    Addr range: 1000..1fff
    tohost addr: none
Input file: hello.elf
    Addr range: 10054..135c3
    tohost addr: none
PC reset: 0x1000; RV32; instret limit: 1000000
[Forvis: instret = 0; MTIME = 2]
inum:1  pc 0x1000  instr 0x297  priv 3  AUIPC
inum:2  pc 0x1004  instr 0x2028593  priv 3  OP_IMM
inum:3  pc 0x1008  instr 0xf1402573  priv 3  SYSTEM_CSRR_S_C
inum:4  pc 0x100c  instr 0x182a283  priv 3  LOAD
inum:5  pc 0x1010  instr 0x28067  priv 3  JALR
inum:6  pc 0xffffffff80000000  instr 0x0  priv 3  NONE
Fetch Trap:exc_code_instr_access_fault
Stopping due to self-loop at PC 0; instret = 6
PASS
Repeating all console output:
--none--
Final value of mtime: 8
rsnikhil commented 6 years ago

All the RV32 and RV64 tests found in the repo, at:

Test_Programs/riscv-tests/isa/

are copied as-is from the following flow:

    $ git clone https://github.com/riscv/riscv-tools.git

... follow the directions in riscv-tools/README,
... which builds into a directory called <PREFIX>/riscv

Copy the tests from:
        <PREFIX>/riscv/riscv64-unknown-elf/share/riscv-tests/isa/

So: I didn't explicitly set any compiler/linker flags myself, just followed the above procedure. You'll have to poke around in their Makefiles to see what compiler/linker flags they used, and replicate them for your own compiles.

In the above builds, note that it compiles all the tests into addresses 0x8000_0000 onwards, which is where you're encountering a trap. Forvis has a 'boot ROM' at 0x1000 which executes about 5 instructions before jumping to 0x8000_0000; in your case, it looks like there is not a legal instruction there, and so it traps.

ghost commented 6 years ago

Thanks for your answer,

Would you accept a pull request that adds an extra program option, so that we jump to the location of the _start symbol, if found in the elf file, instead of 0x80000000?

best regards,