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rsnikhil / RISCV_Piccolo_v1

Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
MIT License
33 stars 5 forks source link

Occur error when run benchmark by using own riscv-tool compiler #1

Open frankhuang014 opened 7 years ago

frankhuang014 commented 7 years ago

I am trying to run others benchmark, but i got some error shown as following

77712: ERROR: CPU.fa_stage1: illegal instruction 77713: fav_do_riscv: pc 0x1c0 instr 0xaaaaaaaa v1 0xaaaaaaaa v2 0xaaaaaaaa m_v_csr tagged Invalid result: Result [ILLEGAL_INSTRUCTION] 77713: ERROR: CPU.fa_stage1: illegal instruction 77714: fav_do_riscv: pc 0x1c0 instr 0xaaaaaaaa v1 0xaaaaaaaa v2 0xaaaaaaaa m_v_csr tagged Invalid result: Result [ILLEGAL_INSTRUCTION] 77714: ERROR: CPU.fa_stage1: illegal instruction ....

I clone the riscv-tools from git@github.com:riscv/riscv-tools.git, than do: $ git checkout 65da94f $ git submodule update --init --recursive $ ./build-rv32im.sh

and compile hello to elf: $ riscv32-unknown-elf-gcc -o hello hello.c

Could you provide your riscv environment for me?

Thanks a lot!

muneebullashariff commented 5 years ago

Hi RSnikhil,

My name is Muneeb and I am from India. I am a Tech Lead with more than 4 years of experience in Front-end verification having expertise in SystemVerilog and UVM. Also, I have good knowledge of computer architecture.

I came across a few projects of yours on RISC-V. If there is anything, in regards to verification of RISC-V processor, I can be of help.

I would like to talk to you with this regard. Please do contact me on my email id: muneeb.mirafra@gmail.com.

I'll be looking forward to your humble response.

Regards, Muneeb