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Fine grained concurrency on thumbv6m (no BASEPRI). #56

Closed perlindgren closed 2 years ago

perlindgren commented 2 years ago

The Cortex-m0/m0+ architecture is getting increasing attention, cheap, light-weight and low-power. While RTIC currently supports the m0/m0+, the locking mechanism implemented is course grain, essentially disabling interrupts globally when a resource is held. This approach is very simple and robust, but looses out when it comes to concurrency, and thus real-time performance.

In our early work on RTFM, the principles for implementing an SRP based scheduler on the v6m architecture was proposed.

A similar approach has been implemented is available in the m0 branch.

Please try, feedback appreciated.

/Per

perlindgren commented 2 years ago

Implemented and merged to master.