Currently, when cycles patterns are just partly correct for one screen, the screen isn't displayed even if the correct part makes sense.
For instance, in the "set time" screen of the bios, NBG2 is configured as 256 colors cell mode with 2*2 character patterns and no reduction:
In this configuration, the screen needs 1 Pattern Name Data (PND) access and 2 Character Pattern Data (CPD) access to the VRAM, which is the case.
Cycle patterns are configured by the system as 0x2F66FFFF in bank B0, meaning Pattern Name Data (PND) access in T0, and Character Pattern Data (CPD) access in T2 and T3:
According to the doc, when T0 is used by a PND read for NBG0 and NBG1, there's no timing restrictions for CPD reads, but restrictions apply for all the others.
So when referring to the restriction table with NBG2 PND read in T0, CPD reads should only be possible for T0-T2 and T4-T7 timings, and T3 CPD read should not be possible :
But the screen is correctly displayed on the console.
Currently, when cycles patterns are just partly correct for one screen, the screen isn't displayed even if the correct part makes sense.
For instance, in the "set time" screen of the bios, NBG2 is configured as 256 colors cell mode with 2*2 character patterns and no reduction:
In this configuration, the screen needs 1 Pattern Name Data (PND) access and 2 Character Pattern Data (CPD) access to the VRAM, which is the case. Cycle patterns are configured by the system as 0x2F66FFFF in bank B0, meaning Pattern Name Data (PND) access in T0, and Character Pattern Data (CPD) access in T2 and T3:
According to the doc, when T0 is used by a PND read for NBG0 and NBG1, there's no timing restrictions for CPD reads, but restrictions apply for all the others. So when referring to the restriction table with NBG2 PND read in T0, CPD reads should only be possible for T0-T2 and T4-T7 timings, and T3 CPD read should not be possible :
But the screen is correctly displayed on the console.