I'm adding a RISC-V backend to chibicc and have made some progress. Just in case anyone is interested, I would like to mention this work here. The commit history of this fork is (almost) the same as the original project, only the codegen related code has been ported to RISC-V instead of x86-64. It uses Spike to simulate compiled programs, so you don't need a RISC-V machine to run it.
Hi there!
I'm adding a RISC-V backend to chibicc and have made some progress. Just in case anyone is interested, I would like to mention this work here. The commit history of this fork is (almost) the same as the original project, only the codegen related code has been ported to RISC-V instead of x86-64. It uses Spike to simulate compiled programs, so you don't need a RISC-V machine to run it.
Repo: https://github.com/ksco/chibicc-riscv
Hope to hear your suggestions.