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rust-embedded / cortex-m

Low level access to Cortex-M processors
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Not enough interrupts #529

Open thejpster opened 2 months ago

thejpster commented 2 months ago

In the Armv8-M architecture, the NVIC supports up to 496 general-purpose interrupt lines. However, processor implementations may limit the maximum to a lower number, often 240 or 480. Cortex-M processors let system designers choose any number of general-purpose interrupt lines appropriate to their system, up to the specified limit. In Cortex-M processors that include the Mainline extension, system designers can choose the number of bits implemented in the programmable priority value for each exception.

-- https://documentation-service.arm.com/static/64c7832738511951cb7a246e

We only allow up to 240 interrupts in this crate, but Armv8-M allows up to 496 (plus 16 exceptions to make 512 table vector entries in total).

adamgreig commented 2 months ago

Thanks, we'll need to update this in cortex-m-rt. Related to https://github.com/rust-embedded/cortex-m/issues/332.