Closed japaric closed 5 years ago
Great first go at it!
It's worth mentioning you also need a memory barrier (DMB/DSB) when using devices with caches such as Cortex-M7's DCACHE, since the main SRAM is in general not coherent between the CPU and DMA.
Edit: You could also use explicit cache management to only invalidate the buffer in question instead of the whole memory, but it requires more careful management.
@adamgreig added a note about caches
If there are no more questions or requests then I think we can land this first version of this chapter.
Good write-up - Thanks
bors r=adamgreig
This is a first draft on building memory safe DMA abstractions.
r? @rust-embedded/resources cc @korken89 @jamesmunns