dma: Mention store-buffer reordering on Cortex-M7

[dnadlinger]

The section on memory barrier requirements for DMA previously suggested that memory barriers are only required when using the data cache. This is not the complete story, as reordering can still occur in the write buffer.

The details will depend on how the involved memory is marked (Normal/Device/…), but a common case where barriers will be needed on e.g. a STM32H7x3-series chip is when interfacing with the Ethernet DMA engine. Even if the dcache is disabled, a barrier will be needed before updating the DMA tail pointer to ensure the driver's writes to the newly-queued packet buffer and buffer descriptor will be seen by the hardware.

I'm not sure whether a more thorough explanation would be in scope here, since it depends on platform details, but with this change, readers are at least made aware of the issue. (We recently stumbled over this in an open-source hardware/software project, see https://github.com/quartiq/stabilizer/issues/33.)

[rust-highfive]

Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @therealprof (or someone else) soon.

If any changes to this PR are deemed necessary, please add them as extra commits. This ensures that the reviewer can see what has changed since they last reviewed the code. Due to the way GitHub handles out-of-date commits, this should also make it reasonably obvious what issues have or haven't been addressed. Large or tricky changes may require several passes of review and changes.

Please see the contribution instructions for more information.

[therealprof]

bors r+

[bors[bot]]

Build succeeded

• continuous-integration/travis-ci/push

[dnadlinger]

For reference, in case anyone comes across this in the future, I just came across a concise table in the Cortex-M7 user guide that confirms this: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0646a/CHDHHFCC.html.