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rust-embedded / riscv

Low level access to RISC-V processors
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fix critial section implementation #121

Closed tfx2001 closed 1 year ago

tfx2001 commented 1 year ago

It should be 0b1000 rather than 0b100. Bit 2 is a reserved bit, and Bit 3 is MIE that needs to be cleared.

image

tfx2001 commented 1 year ago

Nice find and fix thanks! Could you please add CHANGELOG entry?

Done.

dkhayes117 commented 1 year ago

bors r+

bors[bot] commented 1 year ago

Build succeeded: