rust-embedded / riscv

Low level access to RISC-V processors
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Add FENCE.I instruction #127

Closed rmsyn closed 1 year ago

almindor commented 1 year ago

Actually sorry, I forgot. Could you please add a CHANGELOG entry?

almindor commented 1 year ago

Sorry I should've realized this would conflict due to the changelogs, could you rebase with master now that the other fence PR is merged please?

almindor commented 1 year ago

bors r+

bors[bot] commented 1 year ago

Build succeeded: