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rust-embedded / riscv

Low level access to RISC-V processors
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`sip` register set / clear functions #130

Closed PitiBouchon closed 1 year ago

PitiBouchon commented 1 year ago

There are many functions for the sie register to set and clear bits but nothing for the sip register which can only be read I don't know why but it would be super useful (for example if you want to clear the STIP bit to acknowledge a supervisor timer interrupt

romancardenas commented 1 year ago

I'll check this in depth, but I'm 99% sure that usually you don't clear the interrupt pending flags directly from the sip register. Instead, you interface the interrupt controller of your particular target (e.g., CLINT, PLIC, ...).

romancardenas commented 1 year ago

Hmm, it seems weird to me that mip allows you to clear/set the interrupt pending bits whereas sip does not... @rust-embedded/riscv any insights about this difference?

PitiBouchon commented 1 year ago

I'll check this in depth, but I'm 99% sure that usually you don't clear the interrupt pending flags directly from the sip register. Instead, you interface the interrupt controller of your particular target (e.g., CLINT, PLIC, ...).

Okay thx, I misunderstood something

romancardenas commented 1 year ago

No problem! Check this old issue, maybe it helps you with your use case :)