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rust-embedded / riscv

Low level access to RISC-V processors
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scause: add missing LoadMisaligned #138

Closed orangecms closed 1 year ago

orangecms commented 1 year ago

See table 4.2 in privileged spec version 20211203 as found today at https://riscv.org/technical/specifications/

almindor commented 1 year ago

See table 4.2 in privileged spec version 20211203 as found today at https://riscv.org/technical/specifications/

Sorry, I always forget before approving, could you please add a CHANGELOG entry?

orangecms commented 1 year ago

sure - done 🥳