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rust-embedded / riscv

Low level access to RISC-V processors
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Rework of mcause and scause registers #139

Closed romancardenas closed 1 year ago

romancardenas commented 1 year ago

I did a rework of mcause and scause registers to follow the latest RISC-V specification. Namely, I removed the user-level interrupt sources and fixed a missing exception type in scause.

I also used the From and TryFrom traits, so now the Interrupt and Exception enumerations are more usable. I plan to re-export these enums in riscv-rt to avoid code duplicates and simplify a bit the logic of the runtime.