Rework on misa and mstatus

rust-embedded / riscv

Low level access to RISC-V processors

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Rework on misa and mstatus #142

Closed romancardenas closed 11 months ago

romancardenas commented 11 months ago

Added new fields to mstatus register according to the latest RISC-V specification. For RISCV-32, some of the new fields are in a new register, mstatush.