Closed SoulSharer closed 1 week ago
Hi! I don't think we have plans to add this functionality right now. If you think this feature is useful, feel free to open a PR/RFC and we can discuss it further :)
In my opinion, we should look at how cortex-m
deals with platform-specific interrupts and follow their approach.
While working on #200, I've been thinking on how to provide this functionality. I propose the following approach:
PROVIDE
directives) for interrupt and exception sources_start_trap_rust
, __INTERRUPTS
, __EXCEPTIONS
, _vector_table
...). Additionally, the code will provide weak symbols to all these interrupts using global inline assembly.riscv-rt
will use this new macro to generate a code that would be equivalent to its current version. I expect this change not to be a breaking change.my-riscv-specific-rt
runtime crate would have riscv-rt
as a dependency, re-exporting everything and calling to the interrupt macro accordingly to the exception codes of the target.
Are there any plans to provide support for platform specific extensions in
riscv
crate? Reading through RISC-V Privileged Architectures specification I see that there are cases where, for example, a3.1.15 Machine Cause Register
has exception codes allocated for platform and custom use.Was wondering if it would be possible to extend enums
Interrupt
andException
from outside of theriscv
crate itself. The best I could came up thus far is adding "PlatformSpecific1-32" fields toInterrupt
and creating a user-defined enumPlatformInterrupt
with conversion between (TryFrom<Interrupt> for PlaftormInterrupt
) where applicable. (same goes forException
)