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rust-embedded / riscv

Low level access to RISC-V processors
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add `riscv-semihosting` #170

Closed romancardenas closed 8 months ago

romancardenas commented 8 months ago

I adapted riscv-semihosting to the current fashion and added it to the workspace.

The idea is that, by default, it assumes we run in machine mode (the same as in riscv and riscv-rt). The u-mode feature is used to cause exceptions if machine mode is not accesible.

I'm currently using it in my rtic branch for testing in QEMU and works as expected.

MabezDev commented 8 months ago

Is there a reason to not use the semihosting crate? It looks like it already supports RISCV, along with other arches.

romancardenas commented 8 months ago

To be honest, I didn't know this crate existed. It looks more complete than this PR, and it works perfectly in my rtic branch.

The only reason I would accept this PR is to provide the exact same interface as cortex-m-semihosting, which seems to be regularly used in the books, examples etc. The semihosting crate has numerous feature gates to enable more semihosting functionalities depending on your use case.

What do you think about maintaining riscv-semihosting to mimic the cortex-m environment but leaving a section in the README.md file stating that the semihosting crate is way more complete and preferred for more professional development?