Make fence operations safe

rust-embedded / riscv

Low level access to RISC-V processors

818 stars 160 forks source link

Make fence operations safe #180

Closed jsgf closed 6 months ago

jsgf commented 6 months ago

sfence.vma, fence and fence.i just add ordering constraints load/store operations (between themselves, or other kinds of memory access). There's no risk of any UB or other unexpected visible changes in machine state, so we can make these "safe".

Fixes https://github.com/rust-embedded/riscv/issues/179

romancardenas commented 6 months ago

Looks good to me!! Please, update the CHANGELOG.md file to record your changes

jsgf commented 6 months ago

Done