While testing the new v-trap implementation from https://github.com/rust-embedded/riscv/pull/200 I noticed that upon trapping a vectored interrupt, the program counter ends up halfway between instructions right before _start_DefaultHandler_trap causing an illegal instruction exception.
The cause seems to be that this location (_start_DefaultHandler_trap) is reached via direct unconditional jump in _continue_interrupt_trap and the jump instruction is taken at 4-byte alignment. Setting these symbols to .align 4 fixes the problem on our (custom) machine.
I think it's a feature of RISC-V unconditional jumps that they can't express addresses below 4-byte alignment but it could be a feature(bug) of our machine as well. I'm a bit confused about this still because the disassembly shows the correct target j 119a <_start_DefaultHandler_trap> while the machine ends up jumping to 1198 and failing.
While testing the new v-trap implementation from https://github.com/rust-embedded/riscv/pull/200 I noticed that upon trapping a vectored interrupt, the program counter ends up halfway between instructions right before
_start_DefaultHandler_trap
causing an illegal instruction exception.The cause seems to be that this location (
_start_DefaultHandler_trap
) is reached via direct unconditional jump in_continue_interrupt_trap
and the jump instruction is taken at 4-byte alignment. Setting these symbols to .align 4 fixes the problem on our (custom) machine.I think it's a feature of RISC-V unconditional jumps that they can't express addresses below 4-byte alignment but it could be a feature(bug) of our machine as well. I'm a bit confused about this still because the disassembly shows the correct target
j 119a <_start_DefaultHandler_trap>
while the machine ends up jumping to1198
and failing.